1. Field of the Invention
The present invention relates to semiconductor associative memory devices. More specifically, the present invention relates to semiconductor associative memory devices having content addressable memory cells with bit matching function.
2. Description of the Background Art
FIG. 1 is a schematic block diagram of a conventional system employing an associative memory, and FIG. 2 is a schematic block diagram showing the whole structure of the associative memory.
First, referring to FIGS. 1 and 2, the use of the conventional associative memory will be described. Referring to FIG. 1, a main memory 20 and a cache memory 40 are connected to a CPU 100 through a data bus 50 and an address bus 60. A dynamic RAM or a magnetic disk device having relatively slow access time but larger capacitance, which is inexpensive, is used as the main memory 20. On the other hand, an associative memory which has smaller capacitance but faster access time, which is expensive, is used as the cache memory 40. The cache memory 40 is provided to shorten the access time of the main memory 20, in which, of the data stored in the main memory 20, those which are high in access frequency are stored together with the addresses thereof. The writing and comparing operation of the cache memory 40 are controlled by a memory controller 30.
In a system structured as described above, the cache memory 40 is accessed prior to the access of the main memory 20 by the CPU 100. More specifically, when an address signal is outputted onto the address bus 60 from the CPU 100, the cache memory 40 is controlled by the controller 30, whether the address corresponding to the address signal is stored or not in the cache memory 40 is checked, and when the corresponding address is stored in the cache memory 40, a hit signal is outputted from the cache memory 40 to be applied to the memory controller 30. When the hit signal is applied from the memory controller 30 to the CPU 100, data is read from the corresponding area of the cache memory 40 where the address corresponding to the output address signal have been stored. If the address corresponding to the address signal outputted from the CPU 100 is not stored in the cache memory 40 and therefore no hit signal is applied, then the main memory 2 is accessed to read data.
The cache memory 40 formed of an associative memory shown in FIG. 1 comprises a plurality of writing/comparing controlling portions 401, 402 . . . 40n arranged in the column direction and memories 411, 421. . . 4m1, 412, 422 . . . 4m2, 41n, 42n . . . 4mn arranged in the row direction corresponding to respective writing/comparing control portions 401, 402 . . . 40n. The writing/comparing control portions 401, 402 . . . 40n are controlled by a writing/comparing controller 45.
Bit lines are connected to respective memory cells 411 to 4mn in the row direction. Each of the memory cells has, besides the usual writing and reading function, a bit matching function for collating data stored in the memory cell with a retrieval data externally applied to determine whether they are matching with each other. If the externally applied retrieval data matches the stored data, a match signal is outputted on a match line. The match signal is inputted to an OR gate 46 and a hit signal is outputted in turn from the OR gate 46.
FIG. 3 is a schematic diagram of a conventional content addressable memory cell disclosed in, for example, IEEE Journal of Solid-State Circuits, Vol. SC-7, pp. 366. As shown in FIG. 3, the content addressable memory cell comprises a combination of five n channel MOS transistors 1 to 5. The n channel MOS transistor 1 has its drain connected to a bit line 6, its gate connected to a word line 8 and its source connected to a gate of the n channel MOS transistor 3. The n channel MOS transistor 2 has its drain connected to an inversion bit line 7, its gate connected to the word line 8, and its source connected to a gate of the n channel MOS transistor 4.
The n channel MOS transistor 3 has its drain connected to a bit line 6 and its source connected to a control terminal 9. The n channel MOS transistor 4 has its drain connected to the inversion bit line 7 and its source connected to the control terminal 9. The n channel MOS transistor 5 has its drain connected to the control terminal 9 and its source and gate are connected to the match line 10.
FIGS. 4 and 5 are timing diagrams for illustrating the operation of the content addressable memory cell shown in FIG. 3.
The writing operation will be described in the following with reference to FIG. 4. In the writing operation, the data to be written is applied to the bit line 6, the inverted data thereof is applied to the inversion bit line 7, and the word line 8 is brought to an "H" level, as shown in FIG. 4 (a). When the data to be written is at the "H" level as shown in FIG. 4 (b), an "H" level signal is applied to the bit line 6 as shown in FIG. 4 (c) and an "L" level signal is applied to the inversion bit line 7 as shown in FIG. 4 (d). The n channel MOS transistor 1 becomes conductive responsive to the "H" level of the word line 8, and the "H" level data on the bit line 6 is stored in a gate capacitance of the n channel MOS transistor 3 through the n channel MOS transistor 1 as shown in FIG. 4 (e). In the similar manner, the n channel MOS transistor 2 becomes conductive responsive to the "H" level of the word line 8 and the "L" level data is stored in the gate capacitance of the n channel MOS transistor 4 through the n channel MOS transistor 2, as shown in FIG. 4 (f).
The matching operation will be described in the following with reference to FIG. 5. First, the match line 10 is precharged, a retrieval data is applied to the bit line 6 and the inverted data thereof is applied to the inversion bit line 7, and the matching operation is thus carried out. When the stored data does not match the retrieval data, the match line 10 is discharged. When the stored data matches the retrieval data, the match line 10 is not discharged.
Let us assume a case in which the stored data is at the "H" level, an "H" level signal is stored in the gate capacitance of the n channel MOS transistor 3 as shown in FIG. 5 (a), an "L" level signal is stored in the gate capacitance of the n channel MOS transistor 4 as shown in FIG. 5 (b) and the n channel MOS transistor 3 is turned on while the n channel MOS transistor 4 is kept off. When an "H" level signal such as shown in FIG. 5 (c) is applied as the retrieval data, the bit line 6 becomes "H" level and the inversion bit line 7 becomes "L" level, then the control terminal is brought to the "H" level as shown in FIG. 5 (f) and the match line 10 is not discharged, as shown in FIG. 5 (g).
Meanwhile, when the stored data is at the "H" level as in the above described example, a "L" level signal is applied as the retrieval data, the bit line 6 becomes "L" level and the inversion bit line 7 becomes "H" level, then the n channel MOS transistor 3 is turned on while the n channel MOS transistor 4 is kept off. On this occasion, the control terminal 9 becomes "L" level. The match line 10 is discharged by a discharging path of the n channel MOS transistors 5 and 3 and the bit line 6.
Similarly, when the stored data is at the "L" level, and the retrieval data is at the "H" level, then the control terminal 9 becomes "L" level, the match line 10 is discharged by the discharging path of the n channel MOS transistors 5 and 4 and the inversion bit line 7. If the retrieval data is at the "L" level, the control terminal 9 becomes "H" level and the match line 10 is not discharged.
When "H" level signals are applied to the bit line 6 and the inversion bit line 7, the control terminal 9 becomes "H" level regardless of the value of the stored data. This state corresponds to a masked state in which matching is not carried out.
As described above, in the matching operation, the match line 10 is discharged when the stored data does not match the retrieval data. The match line 10 is not discharged when the stored data matches the retrieval data or when it is in the masked state.
In the reading operation, the bit line 6 and the inversion bit line 7 are discharged to the "L" level, and thereafter the match line 10 is brought to the "H" level. When the stored data is at the "H" level, for example, the potential on the bit line 6 rises through the n channel MOS transistors 5 and 3 by setting the match line 10 at the "H" level, since the n channel MOS transistor 3 is in the on state. Therefore an "H" level stored data is read.
On the contrary, when the stored data is at the "L" level, the potential on the inversion bit line 7 rises through the n channel MOS transistors 5 and 4 by setting the match line 10 at the "H" level, since the n channel MOS transistor 4 is in the on state. Therefore the "L" level stored data is read.
Since the content addressable memory of a conventional semiconductor associative memory device is structured as described above, refreshing operation must be frequently carried out to maintain the data stored in the gate capacitances of the transistors 3 and 4.